1. Field of the Invention
The invention relates generally to systems and methods for transferring data in a multiprocessor system, and more particularly to systems and methods for transferring data using a ring bus architecture in a system that implements multiphase clocking.
2. Related Art
When integrated circuits such as processors are operated, they draw current from a power source. The logic components within an integrated circuit typically operate based on a clock signal, so the current drawn by the integrated circuit may suddenly increase at certain points in the clock cycle (e.g. at the rising edge of each clock cycle.) The high rate of change of the current (high di/dt) may cause electromagnetic interference (EMI) and/or noise in the power supply. Both EMI and power supply noise are undesirable.
Reducing EMI and power supply noise is becoming more and more important in designing electronic systems. This is true for a number of reasons. For instance, because it is desirable to increase the number of operations that can be performed by processors in a given amount of time, clock frequencies are increasing. The increased clock frequencies make the processors more susceptible to EMI and power supply noise. It is also desirable to design integrated circuits to use less power, so power supply voltages are decreasing. These decreased power supply voltages also make the integrated circuits more susceptible to EMI and power supply noise. Still further, because it is desirable to increase computational power, processors may include multiple processor cores, each of which contributes to di/dt and thereby creates more noise and EMI.
In some multiprocessor systems, it has been proposed to implement multiphase clock schemes (see U.S. Patent Application Pub. No. 20080141062; Ser. No. 11/609,794.) In these systems, the different processor cores operate on clock signals that have different phases. By shifting the phases of the clock signals with respect to each other, di/dt can be reduced. This reduction in di/dt, however, is obtained at the cost of added complexity in the system's implementation. One complication that arises from the use of multiphase clocking relates to the transfer of data among the processor cores.
Multiprocessor systems often use a ring bus architecture to transfer data between the different processor cores because of the simplicity and scalability of such an architecture. In a ring bus architecture, each processor core is connected to a circular (ring) bus. Data can be put on the bus by an originating processor core, and the data circulates around the ring until it reaches a destination processor core which reads the data off the bus. Some ring bus architectures include a first ring (data path) which enables the clockwise circulation of data and a second ring which enables counterclockwise circulation of data. These bidirectional ring bus architectures have not previously been implemented in systems that use multiphase clocking for elements of the bus and/or interfaces to the bus. One reason for this is that the different clock signals used by the different processor cores may not allow enough time for data to be reliably transferred around the ring, particularly in both clockwise and counterclockwise directions.
It would therefore be desirable to provide systems and methods for implementing a bidirectional ring bus architecture in a system such as a multiprocessor that uses multiphase clocking.